Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
Hi YY,
BTW, can you help me to ask JESD204B designer what 8B/10B protocol does he/she use in the RTL since I cannot figure out the output pattern because RTL in that portion is encrypted? I can find out 10B in the serial bus based on tx_link_clk_clk clock cycle, but no matter how to shift location, and I cannot find the pattern matches Wikipedia 8b/10b encoding. Maybe he/she jump to use. Since I cannot access IEEE JESD204B std, is it possible to give me some hint? He/she can give me the example during input is 0 (zero) in the JESD204B AV bus and what do expect value output in serial bus.
From I analyze your JESD RTL and waveform, I think what he/she design way is feed 64 bus through JESD204B AV bus; then, the logic split up and low 32 bits bus. After that, the serial bus will first send out low 32bits through 8b/10B and converted to 40bits. From the RTL, he/she uses the little endian tech.
I also file the case for 8b/10b issue.
Thanks,
-Fred
Occasional Contributor
