Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
Hi YY,
I don’t ASML policy, so I cannot give you the design files. Timing report and sdc files should be fine. Which file for the timing? Would you think it is useful if you don’t have design file to solve this issue? Can you image which ways you can solve the issue without these files. As I know Synopsys did support without design files in lot of cases since I stay there for a long time, can you image to solve this issue?
The reason that I raise this issue because bank 3C timing has huge different with another bank 3D when I use GPIO cells. I use the device which is 10AX027H4F34I3SG. In addition, as I remember when I did Xilinx FPGA in Cisco, I used “loc” command to fix the I/O timing in the IOB cell. Do you have similar methods in Altera, so I can bypass the issue?
Thanks,
-Fred
Occasional Contributor
