Timing Constraint on SoC HPS Memory

Hi Johnson,

Firstly, may I know which Quartus version and SoC device are you currently working on?

Is it possible for you to share the message that you are seeing or screenshot? Which ever is easy for you, so that I can check what type of message is to be ignored.

Yes, timing constraints are fixed for both dedicated HPS I/Os for Cyclone V SoC and Arria 10 SoC you do not need to define it.

You may refer below for more information regarding the timing constraints on our SoC devices (refer Table 7 on both links )

Cyclone V SoC:

https://www.intel.com/content/www/us/en/programmable/documentation/doq1481305867183.html#qpb1481303809420

Arria 10 SoC:

https://www.intel.com/content/www/us/en/programmable/documentation/pde1458159073865.html#pde1458163562367

Thanks.