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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

Hello everyone, I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the outp...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Lambart,

Answer to your questions is it depends , i wont be able to provide the high level answer here like yes or no. Instead would it possible to share the design ? I will check your LVDS bank mapping and will help me to come to an conclusion .

Thank you ,

Regards,

Sree