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gongmh's avatar
gongmh
Icon for New Contributor rankNew Contributor
2 years ago
Solved

the question about Whether the pin polarities of the FPGA are interchangeable PN

Hello， I use the FPGA:10AS032E2F29I2SG designing the schematics, When the PCB is routed, the P-N polarity of the serdes needs to be changed. But I'm not sure if it supports it? Can you tell me? I...
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EthanLi's avatar
EthanLi
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi gongmh,

​

There is an option RX Polarity Inversion in the Transceiver PHY IP which can invert the data input in the instance generated by this IP. You should enable the polinv port at the same time. And the polinv port will have bit width equal to number of channels used. It is used to invert P and N of data lines, but not clock.

Please refer to :https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/rx-polarity-inversion.html


Thanks,

Ethan