Honored Contributor
Honored ContributorHi David,
the reference design only shows how to interface the ADA card using HDL code in Quartus II. I now want to us the embedded processor NiosII, hence I need to setup a SOPC system. My major concern is about the clocks: As the ADA card is able to, I want to output data with the max rate of 125MSPS. But the default NiosII system clock is only 100MHz. Does this mean by using NiosII I actually sacrifize speed? Can I increase the processors system clock frequency? Additionally I want to synchronize the Analog outputs via ADA with the Digital outputs via GPIO0/1. I expect the GPIO is updated with the system clock but the ADA output comes with the 125MHz PLL clock (generated directly in HDL, i.e. Quartus, by PLL Megafunction as shown in the reference design). What do I have to do in the SOPC system to get the 125MHz PLL clock accessible in the NIOS C/C++ code? Or - as the processor is not that fast - can I forward the processor system clock to the ADA card? Another approach could be to use Nios to generate a look-up table with all analog and digital data and afterwards output it synchronously via Quartus. How could I store (Nios) and access (Quartus) such a file? Thanks, regards, Herbert
