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Altera_Forum
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15 years ago

termination of jtag signals

I am developing a development board for CPLD EPM7064S and will be using parallel cable to program the chip.As in byteblaster schematic,i have to use 74HC244 as level translator after 23 pin header so...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Altera documentations (e.g.configuration handbook) is very clear in this respect. You should have a pull-down for TCK and pull-ups for the other signals.