Forum Discussion
Altera_Forum
Honored Contributor
10 years agoThe "best solution" should be determined by the interface logic, eg., use a pattern generator to fill and pattern checker to check the SRAM read data, and then sweep the transmit or capture clock to determine the eye pattern to the SRAM.
You can adjust the clock phase using the ALTPLL_RECONFIG component ... I posted an example here http://www.alteraforum.com/forum/showthread.php?t=46527 Cheers, Dave