Terasic DE2: Lot of jitter with default SOF, SRAM timing problems, related?

I know this is really late, but after spending weeks trying to solve SRAM problems (and finally finding a solution), I want to post in case it's related to your problem.

Newer DE2 boards have SRAM chips ending with "EDBLL" or similar as opposed to the old ones that were just "BLL" or similar (the "ED" is the important part).

These chips are apparently more sensitive to either spikes or reflections on the control lines, which causes random errors throughout memory when writing to the chip.

To solve the problem, I found that someone recommended setting the line terminations to 25 ohm. I found that it actually works better to set the output current strength to 4mA for all control lines (address, WE_N, OE_N, etc.). It solved all my problems.