TerASIC DE2-115 and Custom FPGA Component

The M9K RAM blocks in the FPGA can implement a DP RAM with suitable widths, ie 1 bit write port and 8 bit read port.

What you can't do is to expose a 1 bit interface to the Avalon bus -- needs to be 8, 16 or 32 bit wide.

So, what you should do is to place the DP RAM inside your custom component and expose the 8 (or 16 or 32) read port through the slave interface.