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3LionsCT's avatar
3LionsCT
Icon for Occasional Contributor rankOccasional Contributor
10 months ago

Terasic Atum A3 Nano

Hi, I am working through the getting started manual for this board which is generally pretty good. However there are no examples of how to use the SDRAM or the Ethernet PHY on this board. It is not ...
3rd party board
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
9 months ago

Hi,
as you already found out, there's SRAM_RTL_test project on the support CD. Unfortunately single rate DRAM is no longer supported in Platform Designer, see Replacement for SDRAM controller after V16.1? | Altera Community

Regarding Ethernet connectivity, I presume standard TSE IP in RGMII mode will support the PHY.

3LionsCT's avatar
3LionsCT
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi Frank,

Thanks for taking the time to answer my question

Do you know if there are header files for the TSE that I can use in a bare metal Ashling RiskFree project?