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Altera_Forum's avatar
Altera_Forum
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15 years ago

System ID Mismatch

Hi all,

I'm using Nios II Development Kit Stratix II Edition. In Quartus II v9.1, I download the hardware image (niosII_stratixII_2s60_RoHS) to the FPGA and do an SOPC build. Then I go to Nios II v9.1 and create a new project using "Nios II Application and BSP from Template" option. I'm just trying to run the simple "Hello_World" project. In the new project wizard I select the appropriate .sopcinfo file. I get the new application and BSP projects. I run it and I get the expected result: "Hello from Nios II!"

I can close down Nios II and Quartus II, start up Nios II again and run my project and get the same result.

However, if I close everything down and unplug the power to the dev board, then start everything back up (like I do every morning), reload the same hardware image - I do not run SOPC Builder - then try to run my Nios II software project, I get: "System ID mismatch - actual: 0x......., expected: 0x........".

I'm new to the Altera development environment so maybe I'm missing something but why would powering off the board result in a new System ID? My understanding is if I don't run SOPC Builder the SysId should not change. If anyone knows the answer to this I would greatly appreciate your help as my current work around is to create a new project everytime this happens.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Well I can't say exactly what is going on. However, one thing I've noticed with the new tools (9.1) is that in the Run Configuration dialog, you sometimes have to click on the "Refresh Connections" button (or something like that) so that it goes out and rescans the devices out on the JTAG chain and the corresponding JTAG debugger instances within those devices. Then you can select the device. Try that first and see if it resolves your issue.

    You are correct that the system ID is compiled into your FPGA image. It does not / cannot change unless you regenerate your SoPC system and then recompile your FPGA image.

    One thing you can do as a sanity check when the error occurs is look at what it's reporting as the system ID that it read from the device. Then look at your software files "system.h" inside your BSP folder and see if it matches. You can also check to see that it matches the ID listed in the Run configuration dialog.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi Jake,

    Thanks for the help. After "Refresh Connections" the system id matches. However, it now complains that the timestamps don't match... Strange.

    IK
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Ok, looks like the timestamp problem was my mistake. Looks good. "Refresh Connections" seems to do the trick. Thanks!

    IK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    hi,I am learning altera.and I have encounter the same question as you. soft developmnet environment is quartus II V9.1 and Nios II 9.1 Software Build Tools for Eclipse. I slove timestamp mismatch as follow: firstly,open the project location. then,open .qsf.last, looking the sentence set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:07:48 JULY 13, 2010"

    replace the red part with new time.

    compile,download .sof,it would be ok.

    good luck to you