Stratix V GS DSP Development Kit - XCVR Reference Clock SMA's

Tom -

I've never used one of those SMA clock inputs but that exact circuit is used on many Altera dev kits, so one would ASSUME that it is "correct" and works as intended. But honestly I'm not sure what type of equipment would generate a differential clock compatible with that circuit. The manuals for your dev kit don't give any guidance on that. I'm guessing you could feed just about any diff clock in there and it would work, such as LVDS. The termination would not be perfect, but it would probably work.

Too bad Altera doesn't man this forum with more (any?) employees who could answer questions like this without requiring a service request. SRs typically take time and the results are not available publicly (to help other users) unless Altera decides to post them in the knowledge base. The Xilinx user forum, by comparison, is manned heavily by Xilinx employees and they respond promptly with good answers. Very beneficial for the user community. I wish Altera would discover the benefits of that approach.

I trash Altera pretty frequently on this forum for their deficiencies vs. Xilinx, but I do not see things getting any better. In fact they may be getting worse. Not surprising with Intel now making the calls. My personal opinion is that the slide within Altera started several years ago as they were getting their butt kicked by Xilinx, and more than anything else that's what led to the sellout. Easier to sell than to fix the problems. In the end I think this takeover is going to be a very bad thing for competition in the FPGA space. Time will tell.

Best,

Bob