Altera_ForumHonored Contributor10 years agoStratix V Gen3 x8 Merged Design I am looking to add a BAR register to the "Stratix V Gen3 x8 Merged Design" with IMEM attached to test the Outbound performance . Can any one help with the approach to do this ... I am having proble...Show More
Recent DiscussionsDevice stopped receiving config data: Internal error (0x0000, 0x00000000, 0x1800).Slow Runtime Performance in FIL Implementation on DE2-115 Using EthernetCXL 2.0 support on the NEW Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile)Agilex5 HPS2FPGA usageMandelbrot viewer on Cyclone V - Platform Designer layout