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Altera_Forum
Honored Contributor
12 years agoData from a DE3 board via 8 LVDS channels to a Stratix V board via 8 transceivers.
Each channel takes data from a FIFO on the DE3 and I need it on a FIFO on the Stratix V. The data is 12 bit wide. (I pad zeros while the data is in the FPGAs but will be removing the zeros before transmitting via the link) A tricky mess indeed. And of-course. As fast as possible which is around 1.6Gbps (so technically 1.28Gbps max actual throughput if 8/10b encoding) Thanks Zubair