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Possibly we will eventually have a microcontroller sending data to the FPGA for testing.
We will be working with a TCP core loaded on the FPGA which is wrote in VHDL and the received data to be re-transmitted will be first getting buffered in external RAM so I am just trying to figure out how I can read that data with VHDL.
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Its more likely that you will have;
- Host PC (PCIe root-complex)
- Stratix V PCIe end-point
- PCIe end-point to Avalon-MM master bridge
- DDR3 Controller
- TCP/IP Core
- 40Gbps Core (QSFP+ interface)
- Scatter-gather DMA Core
The job of the scatter-gather DMA core will be to transfer data from the host PC to either the DDR or to the TCP/IP core. The data transfer rates are likely too high to have any sort of microcontroller in the data path.
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I have done that JTAG-to_Avalon-MM tutorial which I thought was a great help and saw the bus transactions in the BFM simulation. Would I have to write and read all of the control signals myself such as waitrequest, byteenable etc. in VHDL ? So I take it that by writing a program to communicate with the SDRAM running on the NIOS is much simpler? :)
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Writing C code or VHDL is simple. Ultimately the appropriate language comes down to "what do you want to do?". Since you're learning, try both, and then you'll understand what it takes.
For example, to understand how to create an Avalon-MM master, write an SPI-to-Avalon-MM master bridge, or a UART-to-Avalon-MM master bridge, and interface a microcontroller SPI port or UART to your DE0-nano board.
Cheers,
Dave
Honored Contributor
