Stratix V Development board with QSFP ports

Possibly we will eventually have a microcontroller sending data to the FPGA for testing.

We will be working with a TCP core loaded on the FPGA which is wrote in VHDL and the received data to be re-transmitted will be first getting buffered in external RAM so I am just trying to figure out how I can read that data with VHDL.

I have done that JTAG-to_Avalon-MM tutorial which I thought was a great help and saw the bus transactions in the BFM simulation. Would I have to write and read all of the control signals myself such as waitrequest, byteenable etc. in VHDL ? So I take it that by writing a program to communicate with the SDRAM running on the NIOS is much simpler? :)