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I have added the SDRAM controller to the qsys and assigned all the pins.
The next step tho I have trouble with and that is how to use it. I have tried that example of writing to the RAM from the host computer via the jtag interface but would like to do it differently.
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Ok, but at least you know the SDRAM interface works now. You need to mentally separate "checking out the hardware" using JTAG from "what I really wanted to do", eg., access SDRAM via a NIOS II processor. Its important to check that your hardware works via something low-level like JTAG before trying to debug some weird "software bug" in NIOS that is actually related to the SDRAM not working.
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How to read and write to the SDRAM with either VHDL code or a NIOS program? Must I specify the RAM address everytime on the address lines or do I just send data on data lines? How then would I read the data at a specific SDRAM location? I have been trying to find an example of how this is done but no success yet.
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You simply write your C code, and create a linker script telling the compiler that the code is supposed to run out of SDRAM, and that your stack(s), heaps, etc., are located at memory addresses that correspond to SDRAM addresses.
Both the JTAG and NIOS II Avalon-MM masters access devices via their addresses. The Avalon-MM protocol takes care of the different timings required by different devices. From the software perspective, you simply think of accessing devices as either a read or a write. This is enough to get you something working. When you need to think about "performance", then you may need to worry about whether some high-performance part of your code needs to be linked to on-chip SRAM, or whether you need a cache controller, or hardware acceleration. For now, just stick with the simple stuff.
The DE0-nano CD has a NIOS example that includes the SDRAM controller. The design was built using Quartus 13.0, so its not too old. Did you look at that example?
Cheers,
Dave
Honored Contributor
