Forum Discussion
Stratix V Advanced Systems Development Kit SW4 Default Settings
The documentation for the stratix v advanced systems development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-stratix-v-advanced.html) seems to be incorrect in regards to the default settings for SW4. What is the correct default settings for that switch? Here is what the documentation illustrates:
https://alteraforum.com/forum/attachment.php?attachmentid=13748&stc=1 I want to set up this board so that it loads the designs stored in flash. According to the documentation, it states that SW4.6 needs to be in the ON position, but switch 6 is for Clock Selection... Thanks, QG36 Replies
- Altera_Forum
Honored Contributor
Is this what you have ?
Revision D. No MoSys 72Mb chips No QDRII+ memory chips populated ? With fattest 5SGXEABN2F45N2 chips instead ? https://alteraforum.com/forum/attachment.php?attachmentid=13843&stc=1 - Altera_Forum
Honored Contributor
Yep. Seems like the same board...Didn't realize that the MoSys and QDRII chips were missing :(. I'll have to go back and inspect the board more carefully as I didn't remove the fan assembly like you did...
- Altera_Forum
Honored Contributor
Just checked the board and it is exactly the same as yours. No MoSys nor QDRII chips, but with the faster and more LE-based FPGA. Do you have any software for the board, other than Quartus? The kit software doesn't seem to work for this board.
- Altera_Forum
Honored Contributor
I am little confused as well, the files on Altera/Intel website contains files for revision C, not D, as it marked on the PCB file, however PLX PCIe switch is on the top side and attached to the heatsink through thermoconductive resin, not like shown on the Altera's photo on the kit's Web page. Rev D actual PCB looks quite similar, I thing almost the same, but need to verify carefully. It has test blind-via pads on the bottom sides for most FPGA's ball pins. There is nothing complicated in this board, just be sure that all memory signals, XCVRs, power, and reset are connected the same way and match with errata chip. Otherwise need modify design files to actual wiring and/or apply errata workarounds if possible.
https://alteraforum.com/forum/attachment.php?attachmentid=13851&stc=1 MoSys chip MSR576 (BE1, first generation) for this board is not available anymore. MSR720, MSR820 are current BE2 (Bandwith engine 2) are available on an expansion board for Xilinx Virtex 7 Ultrascale kits. And it's really quite expensive thing ! Altera's design files for Stratix V Adv. Sys. Dev. Kit doesn't have IP for MoSys as well. I found than no any specific designs examples for this kit are available in Altera design store as well. Could easily solder all QDRII+ chips but it's look not actual in case of fat 5SGXEABN chip with enough internal memory cells. Looks like this board is customized for a specific corp. customer. I bought from liquidator warehouse for a really nothing price for such board especially when actually populated GXEABN is about twice expensive than GXEA7 one. Need to get answer from Altera to clear background behind rev. D board. I don't have any specific files for it as well. - Altera_Forum
Honored Contributor
--- Quote Start --- Seems that my board is a bit different than what is on the Altera website. It doesn't seem to contain a 5SGXEA7N, but a totally different part and hence the BTS doesn't seem to run. It this correct? --- Quote End --- Confirmed. Same on mine. PowerMonitor and ClockControl appear to work, though. - Altera_Forum
Honored Contributor
--- Quote Start --- Is this what you have ? Revision D. No MoSys 72Mb chips No QDRII+ memory chips populated ? With fattest 5SGXEABN2F45N2 chips instead ? --- Quote End --- Seems I have this too. Thanks for finding out the exact FPGA type. I stopped short of removing the heatsink from my board to find out (even without screws, it seems to stick pretty tight). - Altera_Forum
Honored Contributor
--- Quote Start --- Need to get answer from Altera to clear background behind rev. D board. I don't have any specific files for it as well. --- Quote End --- Really interested as well. If the schematic is different than for the retail board, a world of hurt may be waiting ahead. - Altera_Forum
Honored Contributor
--- Quote Start --- I am little confused as well, the files on Altera/Intel website contains files for revision C, not D, as it marked on the PCB file, however PLX PCIe switch is on the top side and attached to the heatsink through thermoconductive resin, not like shown on the Altera's photo on the kit's Web page. --- Quote End --- Seems the retail photos are of an earlier revision than C. I've done a cursory comparison of my/our board and the retail photos, and aside from the U47 position, I only discovered a capacitor around the DC jack in a different position as well. But it all matches the revision C documentation. All in all, I'd say it's pretty likely that the schematic has not changed in any significant way, from revision C to D. - Altera_Forum
Honored Contributor
Guys,
Did you get any answer from Altera for the past few month? Apparently I also purchased this revision from an eBay seller and struggling to make this board at least pass the test. Thank you! - Altera_Forum
Honored Contributor
Hi all,
did anyone get this board working? I believe I bought the same board from the same ebay seller. I contacted Altera about this board and their answer was: > HI Markus, > > Kindly check with Terasic. According to Terasic, this kit is not ship out from Altera. > > Regards, > > Winnie Does this make any sense. The links on the Terasic site are pointing to the Altera website. I am getting confused ...