Stratix IV GX Pin Assignment

Sure the FPGA is able to use the RGMII interface with the PHY, and so is the PHY, but from the schematic (page 13) you can see that the PHY's RGMII interface isn't connected, so you are stuck with SGMII on that board.

You should first ensure you have a correct MDIO communication with the PHY. The MDIO isn't used to transfer packets, but just to configure the PHY and get statistics. Once you have this, you know that the PHY is running.

When checking the PHY's answer on the MDIO but, you must keep in mind that the TSE driver will try all the 32 possible PHY addresses, and will only get an answer on one of theme. Therefore you must either have a very big signaltap memory buffer to be sure to capture all the transactions, or trigger on something more special (such as mdio_oen at 1 and mdio_in at 0 at the some time, which would indicate a PHY communication).

Once you can communicate with the PHY, you can focus on the SGMII interface again.

When you have conflicting information about the pins between the user manual and the schematic, always trust the schematic. Bogus kit documentation is a recurring problem with Altera.