Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Stratix II ES180 board, help me with DAC output

Hi all, I am in trouble with ADC module. I try to code a very simple code: module dac_test( input clk, output [13:0] dac ); assign dac = 14'b11110001010110; endmodule...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

First, if you have a look at the DAC904 datasheet, you will see that the DAC loads the data values on the rising edge of the clock, so it's not a good idea to have a signal pin at the same frequency than your clock. It should be at most half the frequency.

Second if you have another look at the DAC904 datasheet, you will see that TI made something very stupid: they called "Bit1" the MSB and "Bit14" the LSB. So in fact you need to connect your data vector backwards: dac[0] to Bit14, dac[1] to Bit13, dac[2] to Bit12 etc.... right now you are toggling the least significant bits right now, which are unlikely to change the DAC output enough for you to see it on the scope. Try to toggle Bit1 and Bit2 instead, for example, and see if there are any changes.