Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks for the reply
but if this would be the case, wouldn't there be a pin less at the FPGA and one more at the RAM? I linked the manuals in my original questions. Maybe you see what i mean. Plus I need the distinct location of pin A10 for the initialisation sequence. If the location is somehow influenced by the 15-14 pin issue, i can't control the RAM.