Stratix 10 Transceiver Toolkit User Defined Test Pattern

Hi,

There is a 'Data Pattern Generator' block within the E-tile PMA. You choose it to send user-defined data.

Refer for the description: https://www.intel.com/content/www/us/en/docs/programmable/683723/current/data-pattern-generation.html

For related registers and example refer below links:

https://www.intel.com/content/www/us/en/docs/programmable/683723/current/user-defined-pattern-example.html

https://www.intel.com/content/www/us/en/docs/programmable/683723/current/prbs-usage-model.html

You may also want to instantiate the Avalon-St Data pattern verifier block (available in IP Catalog) for validation of received data.

Recommend you to go through XCVR toolkit training video for usage in general.

https://www.youtube.com/watch?v=bwhyJuphy8I

Regards

Hi,

Check section 7 of E-Tile Transceiver PHY User Guide (links in previous comment).

Section 7.3, Figure 98 shows the ports when you enable this feature.

Further sections 7.5 and 7.6 provide timing details on how to access these ports.

Regards

Hello Ash,

thanks for the answer. It helped me clarified my ideas.

However there is still something that bugs me

I see that in the example design that I am using is included (but not used! it is leave unconnected) this IP core "JTAG to Avalon Master Bridge Intel FPGA IP":

And its signal matches with the ones of the E-Tile Native PHY IP core, as in the Figure 98 that you mentioned: 

Browsing on the online documentation, it looks to me that it is possible to use the "JTAG to Avalon Master Bridge Intel FPGA IP" to send some commands directly from the System Console and interacts with the design.

Let's suppose the I connect correctly this IP to the design (now, as I mentioned, is not connected): would it then be possible to access the transceiver PMA registers and program them from the System Console, instead of writing a custom logic (in VHDL/Verilog) to access these registers?

In other words: would it be possible to execute these instructions just by playing with the System Console?

Would you have maybe some design/examples/tutorials in that case? I see that in this thread the user @SyafieqS_Intel send to another user a zip file containing tutorial related to write and read avalon mm using jtag to avalon master bridge. In case I could have access to that, it could be highly beneficial for my project.

Regards,

Enrico

Hi,

I have sent you the files from other thread via e-mail. Please check.

Regards

Hello Ash,

Thanks for the file.

In the meanwhile, I figured it out by myself how to load the User Pattern: I leave some hints here in case it would be useful to somebody.

I used the some of the functions of the script "Ttk_helper_s10tx.tcl" that you can find together with other examples in this link . I managed to send the pattern through System Console commands using these functions.

I didn't have to connect the "JTAG to Avalon Master Bridge Intel FPGA IP" to the rest of the design.

Regards,

Enrico

Hi,

Glad to know that. Closing the case. However, it will be open for community users to comment.

Regards