Forum Discussion
Hi,
Thank you for reaching out to us. I will help you with this.
Can you confirm what the devkit OPN is for this case?
- AqidAyman_Altera1 month ago
Regular Contributor
As per my understanding, even the devkit supports adjustable voltage at VCCIO_FMCA, if you only depopulate R468 to “get 1.2 V,” the regulator’s selection network is left in an invalid state. The kit’s power sequencing/monitor circuitry then detects an under‑voltage/fault and pulls the converter enable (EN) low, so the rail collapses to 0 V. Can you try to follow the resistor settings in the user guide, which leave all of the resistors open to get 1.2V.
Refer here:
https://docs.altera.com/r/docs/683674/current/stratix-10-gx-fpga-development-kit-user-guide/default-switch-and-jumper-settings
- AqidAyman_Altera1 month ago
Regular Contributor
Are you removing all the mentioned resistors, which are R460, R464 and R468? Based on my understanding, you depopulate R468 only.
Correct me if I'm wrong.
If you already done that, I suggest you below steps:
- Ensure R468 is removed and that R460 and R464 are not populated (verify no solder bridges). That yields 1.2 V per the user guide.
- Bring-up check
- Power cycle the kit after changes.
- Verify VADJ at the FMC test point and confirm the Power Good signal remains asserted.
- Test without an FMC card first; then use only FMC cards that support 1.2 V VADJ.
- navgh771 month ago
New Contributor
All 3 resistors R460, R464 and R468 are de-populated, with no FMC card connected, VADJ output is still 0V and the enable signal for that DC-DC converter is low.