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Sri_yerr's avatar
Sri_yerr
Icon for New Contributor rankNew Contributor
4 years ago

Storing bitstream in Startix V GS SI eval kit and transmitting through the transmitter.

Hi, I am using Stratix V GS SI evaluation kit to load bitstreams in the memory and transmit them through the SMA transmitters. Could someone shed some light on how to do it or any design example? ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Srikanth,


Thanks for your clarification that you will be using the transceiver TX to send serial data at 8G to 10G data rate. As I search through the web, there seems to be no specific simple example design on this. I have attached a Modelsim simulation example which was previously from wiki for your reference. To run the simulation, do the following:


1. Extract the ZIP

2. Change the working directory of Modelsim to the ZIP folder

3. Type "source simulation_setup.tcl"

4. Type "simulate" to start the compilation and simulation


Note that this example was targeted for Q15.0. You can try out to see if it still working on your side.


As I looked into the a.v file, it seems like it is connected to a constant pattern generator. You can replace this with your own pattern generator.


It is recommended for you to go through the following documentation for further details on the transceivers prior to performing testing:


1. Stratix V Device Handbook Volume 2: Transceivers - https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-v/stx5_xcvr.pdf

2. V-Series Transceiver PHY IP Core User Guide - https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/xcvr_user_guide.pdf


Please let me know if there is any concern. Thank you.