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Altera_Forum
Honored Contributor
Honored ContributorStartix-III DSP kit, RAM dropping samples
Hi, I connected a 1-port ram to the ADC in my Stratix-III dsp kit. For some reason, every 150 clock cycles or so I drop some samples. I access the ram by using the "in system memory content editor" ...
Altera_ForumHonored Contributor
Honored Contributorwhere does your "clock" signal come from? If it isn't perfectly synchronized with the ADC clock you may loose some signals.
If you are reading the memory contents while your design is still writing in memory then you'll get bad data, probably a mix of old and new samples, and this could explain what you see. You would need to stop writing to the memory once you've reached the last address, and only then read the memory contents.
