SRAM speed on Cyclone III Dev Board

This is the clock frequency, so you multiply by 32 to get the max theoretical bandwidth.

But be careful about two points:[list][*]the first example designs have some of the data signals mapped on the wrong pins on the FPGA. Compare the pin configurations between the schematic and the pin planner[*]the memory isn't a real SSRAM, it is a SDRAM with a SSRAM-like interface. As a result it can have a quite high latency if you don't use bursts (7 cycles at 104MHz).[/list]I wonder why Altera selected this memory on the board, it makes little sense. The main interesting aspect of an SRAM compared to a DRAM is random access time, and you don't have it here.