SRAM K1B3216B2E on Cyclone III Development Kit

Please use an and-logic and a latch for the wait-signal.

Remember the lsb of the tristate address is not connected (tristate bus: 26 bit (25..0), sram and flash bus: 25 bit (24..0).

Timing: Use a pll to generate the 100MHz clock for the avalon bus in SOPC-builder. Generate another 100MHz clock for the SRAM with a phase shift of -3,5ns

The utram is optimised for 100MHz clock. See the documentation in the \ip\utram directory for other timings.

see attachment for wait-logic and assigning the address-bus.