SRAM K1B3216B2E on Cyclone III Development Kit

Hi,

I had a quick look at your code.

A possible pitfall is the bidirectional assignment... here is how it could go wrong:

if B1 and B2 are two bidirectional nodes(inout ports) then any wiring assignment must take into account double driving.

for example:

B1 <= B2;

doesn't mean they are wired up contrary to popular belief. It means B2 is driving B1 but not the other way round

hence you must also add:

B2 <= B1;

You will need appropriate mux to avoid multiple drivers

Kaz

thank you for your quick reply!!!

no, i tried it. that generates an synthesis error:

Error (10666): Bidirectional ports "AvS1DataxDZIO[31]" and "SramDataxDZIO[31]" at SRAMInterface.vhd(36) directly or indirectly feed each other

regards,

reto

It remains crucial that you drive each of your outputs. You can't just drive one of your two inout ports.

It is a matter of the design platform to find out how to drive each output.

You may need to define who is driving who through a mux.

In my project(not a dev board). I interfaced with sdram and flash with bidirctional buses and used double assignment without problem(Quartus 7.2).

The error may be due to occurence of mutiple drivers on a node which is not allowed(a node must have one driver at any given time).

Kaz

May be a quicker way is to redefine the avalon inout as separate in/out then wire up to the bidirectional pin in two assignments. Alternatively use port map which look after the wiring.

kaz

hi kaz

i think it should do, if i only connect the bidir-signals with one <= statement. but i will have a go...

thank you!

reto

so, it still doesn't work, but i am one step further. it's not necessary to connect the tri-state data lines through my custom sopc component, i can take directly the ones from the tri-state bridge...

can anybody tell me, whats going wrong, i attached my .vhd (custom component in sopc builder)... i connected address bit a[0] with a[2] from avalon-mm master, hope this is correct, due to 32-bit data (not 8-bit)

thanks in advance for any assistance!

reto

Hi,

First: you should discard two address LSBs, not three.

Second: you have commented out address and data lines??

third: why using this complex cascade of two tristates ?

If all you need is just do something? for the "wait" signal from sram then why not just port map nios avalon directly to your top project except for doing that something, I don't see any need for this module in the first place.

Why do you do that something in hardware, why not leave it for software as the software is supposed to read/write to sram.

kaz

first: i discard two LSB's --> address line of development board beginns with a1...a21

second: i shared address lines with other peripherals --> setting in tri-state bridge of sopc builder

third: this cascade is really stupid, i deleted it ;-)

your are right, i don't need such a component with a vhdl-file, i built now a component with only one _hw.tcl file --> see attachment

IT STILL DOESN'T WORK and i don't know why?

THANK YOU very much for any help!

Reto

I am not sure about which address you mean starts with a(1) rather than

a(0). You say the "peripheral", it sounds you mean sram address.

You need to discard 2 bits of nios avalon address bus i.e. connect nios avalon address line(2,3,...etc) to all of your sram address lines. But in your previous vhdl, you connect nios address lines(3,4,...etc) to sram and this is wrong.

I am not good at TCL. If you upload your nios entity, top project entity and your instantiation then I may be helpful

kaz

here i am with my top-level entity (.bdf) and sopc-system

thank you kaz for your quick help!

reto