Source Synchronous Interface Output Constraint

1. Generally is yes. Calculating the minimum and maximum board delays between the FPGA and SDRAM based on the trace length is a good starting point and right way to do.

2. The clock's lowest and maximum trace delays can be determined similarly to how the data lines are. The lowest and maximum trace delays for the clock can be calculated using the PCB designer tool and the measured trace length of the clock line. You can also take into account additional elements like the skew between the clock and data lines, the transmission delay through any clock buffers or inverters, and any additional circuits that might impact the clock delay.