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If your suggestion is same as I thought on the above picture, I have tested it.
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I never used the predefined template for ram testing.
I meant you could test it manually:
First of all select onchip memory for running code and program data.
Then in your application set up a loop which writes known data starting from sdram base address. Afterwards read back data and check if is as expected.
Example:
for (i=0; i<0x10000; i++) {
*((int*)SDRAM_BASE_ADDRESS+i) = i;
}
error = 0;
for (i=0; i<0x10000; i++) {
if ( *((int*)SDRAM_BASE_ADDRESS+i) != i ) {
error = i;
break;
}
}
This way you can identify if the problem is always with specific addresses or data, while the jtag debugger simply tells you the address range where the error occurred, but not the exact address neither what the data mismatch was.
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What if there are a little difference in the shift phase?(for example : 0.1ns of difference) will it be any error ?
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A few tenths of ns difference should not matter in your case and with your clock freq.
Probably your design can work with any shift from -1.0ns to -2.0ns
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