SOPC with SDRAM Contoller

Thank you for your reply, Cris :o

I did as you suggested me.. I have made 3 different clocks :

1. 50MHz for CPU_clk

2. 50MHz with -1.46 phase shift for SDRAM_clk in the SOPC

3. 50MHZ for SDRAM_clk_ext and connects it to DE0's SDRAM clk (PIN_E5)

I got below error :

verifying 00800000 ( 0%)

verify failed between address 0x800000 and 0x8002f3

leaving target processor paused

FYI, I did an experiment with this system + on-chip memory , and it works.

It really seems like my SDRAM or PLL doesn't work well, but i dont know what's wrong :eek:

Thank you,

Yuyex:o