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Inside sopc builder, use the same CPU_clk for sdram, too. While SDRAM_clk will be only used externally to connect to the actual sdram chip clock pin.
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Do you mean that I cant separate the clock for CPU and the clock for SDRAM?
I did search for this requirement and it's needed to be separated from the information I have gathered :confused:
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This SDRAM_clk will need a phase shift, in order to meet timing requirements: usually a 1.5ns phase lead relative to CPU_clk is good in most situations.
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I made a calculation based on the formula on the user guide, which lead to -1.46 ... and do you mean
minus 1.5ns?
Thank you,
Yuyex:o
Honored Contributor
