SOPC with SDRAM Contoller

--- Quote Start ---

seems like NIOS didn't take the new SOPC system that i've fixed. So i tried to create a new project file and input the new system once more.

I got below error :

verifying 01000000 ( 0%)

verify failed between address 0x1000000 and 0x100d96b

leaving target processor paused

--- Quote End ---

Something has changed but there's still something wrong if sdram base address is really 0x800000.

Or is it actually 0x1000000?

Do you mind posting the picture of your sopc? So I can see all bus connections and base address

--- Quote Start ---

Besides, I need to ask if i need to assign input/output pin for this SDRAM in this SOPC?

--- Quote End ---

Sure, you must assign sdram pins. But you must do it in Quartus project, not in sopc builder.

If you are a beginner, remember the flow is as follows:

- design the sopc system

- when you generate it, sopc builder creates a black box block with contains the system and exposes the reuired i/o pins (i.e. clock, reset, sdram i/o, PIOs, ...)

- add the sopc block in your Quartus project (as HDL or schematic)

- you must connect the block pins to fpga device pins, adding glue logic if required

- assign the used pins, based on how the actual fpga is connected to external devices (clock, sdram) on your board.

- compile quartus project which creates the .sof configuration file

- create the Nios bsp and application and associate it to your sopc system

- load the fpga configuration

- build and load the Nios application

Regards