Slow frame rate (DE1 + D5M)

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You need just increase the PIXCLK by adjusting the d5m build-in PLL, or connect XCLKIN pin directly to your in-fpga PLL.

In terasic examples XCLKIN is set to 12MHz thru d5m's PLL, but PIXCLK has the same frequency(because of wrong config(I2C_CCD_Config.v))

Example of PLL configuration is in THDB-D5M_Hardware specification.pdf (pages 30-32)

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Thank you,

I modify these two lines in I2C_CCD_Config.v following your help and it works

11 : LUT_DATA <= 24'h116004; // PLL_m_Factor<<8+PLL_n_Divider

12 : LUT_DATA <= 24'h120004; // PLL_p1_Divider

Pixel_clock = 60hex(96decimal) * XCLK(25MHz) / [M(4+1) *N (4+1) = 96MHz

also change the XCLK to camera module to 25MHz.

refer to camera hardware specification in PLL (page 34) for more information.