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Altera_Forum
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15 years ago

SIV PCIe high performance ref design data can arrive out of order

Hi, We've been using the Stratix IV PCIe high-performance reference design for a while and see some funny behavior when performing a read DMA: the data arrives into our logic out of order inte...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi Kevin,

Thanks for the swift reply.

I can understand that multiple outstanding requests could be dealt with out of order to eek out the best performance, but I wonder if they could be dealt with atomically i.e. once it starts pumping out data for a particular tag_id, it can only provide data for that tag until completed, even if a few clock cycles are unused.

Looks like I'll have to delve into the ref design more deeply rather than just using it!

Cheers,

Dwayne