Signaltap waiting for clock on PCIe example design

Hi Wincent,

Thank you for your response.

As I am targeting AGF027 FPGA board, the design uses F-tile.

Please see my comments marked [Binu].

1. Clock Selection: Ensure that you have selected the correct clock for the PCIe Avalon Streaming example. It should be the same clock that drives your Avalon ST interfaces.[Binu] Yes it is the correct clock. It is the coreclkout_hip from the PCIe Avalon streaming IP. Have used this same clock for a P-tile based example design in past.
2. Connection: Verify that the clock signal is correctly connected to the SignalTap instance. Double-check the SignalTap setup to ensure the correct clock is selected.[Binu] As far as I can see, there is no red mark around this clock setup in SignalTap. I am using pre-synthesis selection.
3. Timing: If the clock is gated or not running during the capture, SignalTap may not detect it. Ensure that the clock is active when you start capturing. [Binu] This is something which I am still checking from our hardware setup.
4. Clock Domain Crossing: If there are asynchronous crossings in your design, ensure that the clock domain for SignalTap is correctly set up to capture signals crossing those domains. [Binu] This is not my custom design. It is Altera's PCIe reference design out of the box.
5. Reset: Ensure that any required resets are correctly applied and released to allow the design to start operating. [Binu] This is a good point. It crossed my mind too. Another one to check from hardware setup.

Regards

Binu