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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

Signaltap waiting for clock on PCIe example design

Hi there, I am running PCIe example design on AGF027 development kit. I am running Gen4, 1x16 Endpoint reference design. Using Signal tap to check basic functionality. I ran through the process as m...
Fpga Devkit
  • binupr's avatar
    binupr
    1 year ago

    Hi Wincent,

    Finally narrowed down the issue.

    Issue was that the Switch selection option for PCIe reference clock mentioned in Intel/Altera AGF027 dev kit user guide was incorrect and this led to the clock buffer put in wrong input mode.

    Below is screenshot from User Guide.

    Switch 4.3 should be set to OFF to receive local clock. As you can see the documentation suggests setting to be ON to receive local clock.

    Could you please feed this back to the corresponding documentation team within Intel/Altera to get this updated?

    Thanks

    Binu

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi Binu,


Which Tile you are using for this ? F-tile or P-tile ?

Can you please sent the printscreen error between post-fitting signals and pre-synthesis signals ?


SignalTap showing "waiting for clock" typically means that SignalTap is not detecting the clock signal for the specified clock domain. This could happen due to several reasons:

  1. Clock Selection: Ensure that you have selected the correct clock for the PCIe Avalon Streaming example. It should be the same clock that drives your Avalon ST interfaces.
  2. Connection: Verify that the clock signal is correctly connected to the SignalTap instance. Double-check the SignalTap setup to ensure the correct clock is selected.
  3. Timing: If the clock is gated or not running during the capture, SignalTap may not detect it. Ensure that the clock is active when you start capturing.
  4. Clock Domain Crossing: If there are asynchronous crossings in your design, ensure that the clock domain for SignalTap is correctly set up to capture signals crossing those domains.
  5. Reset: Ensure that any required resets are correctly applied and released to allow the design to start operating.


Maybe you can try to generate a new example design, please ensure that you select the "target devkit" so that all the pin can be assign properly.


Regards,

Wincent_Intel



  • binupr's avatar
    binupr
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Wincent,

    Thank you for your response.

    As I am targeting AGF027 FPGA board, the design uses F-tile.

    Please see my comments marked [Binu].

    1. Clock Selection: Ensure that you have selected the correct clock for the PCIe Avalon Streaming example. It should be the same clock that drives your Avalon ST interfaces.[Binu] Yes it is the correct clock. It is the coreclkout_hip from the PCIe Avalon streaming IP. Have used this same clock for a P-tile based example design in past.
    2. Connection: Verify that the clock signal is correctly connected to the SignalTap instance. Double-check the SignalTap setup to ensure the correct clock is selected.[Binu] As far as I can see, there is no red mark around this clock setup in SignalTap. I am using pre-synthesis selection.
    3. Timing: If the clock is gated or not running during the capture, SignalTap may not detect it. Ensure that the clock is active when you start capturing. [Binu] This is something which I am still checking from our hardware setup.
    4. Clock Domain Crossing: If there are asynchronous crossings in your design, ensure that the clock domain for SignalTap is correctly set up to capture signals crossing those domains. [Binu] This is not my custom design. It is Altera's PCIe reference design out of the box.
    5. Reset: Ensure that any required resets are correctly applied and released to allow the design to start operating. [Binu] This is a good point. It crossed my mind too. Another one to check from hardware setup.

    Regards

    Binu

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 year ago

      Hi Binu,

      Maybe you can check the point no5.
      Do you try to generate an example design by selecting the "target devkit" via IP catalog ?
      If not, I do suggest you to try so.

      Regards,

      Wincent_Intel