Forum Discussion
Occasional ContributorSignaltap waiting for clock on PCIe example design
Hi Wincent,
Finally narrowed down the issue.
Issue was that the Switch selection option for PCIe reference clock mentioned in Intel/Altera AGF027 dev kit user guide was incorrect and this led to the clock buffer put in wrong input mode.
Below is screenshot from User Guide.
Switch 4.3 should be set to OFF to receive local clock. As you can see the documentation suggests setting to be ON to receive local clock.
Could you please feed this back to the corresponding documentation team within Intel/Altera to get this updated?
Thanks
Binu
Occasional ContributorYes I have already tried those experiments. I ran a counter with General Purpose FPGA clock and that is showing as free-running/can trigger a signal tap instance.
Occasional ContributorIn one of the experiments, I tried bringing out the lock from System PLL to an LED and I cannot see it getting asserted. So I do think the System PLL is not locking to these reference clocks. Surely I can think it is a board issue but these boards are from Intel and I see same behaviour on 2 such boards.
My suspicion is whether this is a bug in Quartus 23.4. Something similar to https://www.intel.com/content/www/us/en/support/programmable/articles/000092708.html?wapkw=System%20PLL%20IP.
