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Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Should read request signal in avalon interface be a continously high signal or just a pulse?

Hi, I want to use avalon interface to read the data from DDR to BRAM with a burst size of 512, bit interface is 64. Currently i am sending the read request as a pulse. But i am not sure if it is the...
Sushmita's avatar
Sushmita
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi sstrell,

Yes, i want to read as a master. I am using the signal WAITREQUEST_N. When i run the module on FPGA, the WAITREQUEST_N is always high, irrespective of whether i am issuing a read command or not. I am using a single master.Even In this case should my module be WAITREQUEST_N dependent?

Thank you for your reply.

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Your wait request need to be deassert in the slave itself. without deassert on the slave, you cannot do anythings.

Unless you are using fixed wait states, your wait request need to be deassert. Page 26 base on the link above.