Occasional Contributor
Super ContributorThere is no "read request" signal in Avalon. If you are saying that you are reading from an Avalon slave, as a master, you must honor the waitrequest signal. You can issue a read command to the slave, but you must hold the command active until one clock cycle after waitrequest goes low (unless there's some additional latency parameters set by the slave) at which point the readdata should be available.
See the Avalon spec for details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
#iwork4intel
Occasional ContributorHi sstrell,
Yes, i want to read as a master. I am using the signal WAITREQUEST_N. When i run the module on FPGA, the WAITREQUEST_N is always high, irrespective of whether i am issuing a read command or not. I am using a single master.Even In this case should my module be WAITREQUEST_N dependent?
Thank you for your reply.
Super ContributorYour wait request need to be deassert in the slave itself. without deassert on the slave, you cannot do anythings.
Unless you are using fixed wait states, your wait request need to be deassert. Page 26 base on the link above.
