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Altera_Forum
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16 years ago

SDRAM PLL phase adjustment DE2-70

I'm trying to incorporate the SDRAM into a simple nios system. Following the tutorial it says to have a PLL output a clock with a 3ns phase shift to account for delay with respect to the controller h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks, Sorry I meant "-3ns' as well, it doesn't work and i have tried different values like -2.5 and -3.5... My calculated phase shift does come out positive so i don't know if i'm calculating it wrong or what