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Altera_Forum's avatar
Altera_Forum
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16 years ago

SDRAM PLL phase adjustment DE2-70

I'm trying to incorporate the SDRAM into a simple nios system. Following the tutorial it says to have a PLL output a clock with a 3ns phase shift to account for delay with respect to the controller h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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to have a PLL output a clock with a 3ns phase shift to account for delay with respect to the controller however it doesn't work and I get this error

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The clock for the SDRAM should LEAD with respect to the FPGA clock. The phase shift should be NEGATIVE: -3ns .

Hope this helps...