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Winston_Sun's avatar
Winston_Sun
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5 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.