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Winston_Sun
New Contributor
New ContributorSDC timing constraint cannot be applied during compilation
Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS
Super Contributor
Super ContributorHi Sun,
The order of your file in setting -->general--> files should be sdc at the top of instead of sdc at the latter part.
Can you check if KDB below is applicable?
