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Winston_Sun's avatar
Winston_Sun
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4 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
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4 years ago

Hi Sun,


Apologize for the late response. Can you check the SDC order of the node signal. This could be due to constraint order is specified latter. Make sure the node is not specify latter in the sdc part as this will not take any effect during compilation.





  • Winston_Sun's avatar
    Winston_Sun
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    4 years ago

    Hi,

    yes, that is the problem. What is the general rules for the sdc constraint files order in the qsf file?

    Thanks,

    Winston