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Winston_Sun's avatar
Winston_Sun
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5 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hello Sun,


I can reproduce the issue with latest version as well. Seem this issue look to me like a bug. I am checking this with engineering team for further debug. Will let you know any update on this.