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Winston_Sun's avatar
Winston_Sun
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4 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
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4 years ago

Hi Sun,


Btw, have you tried the origin design, did Quartus ignored the constraint as well? or occur only when you replace the single JESD204C IP block in the intel example design with three separate JESD204C IP blocks (Duplex PHY + Simplex TX MAC + Simplex RX MAC) ? Let me know this as well.