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Winston_Sun's avatar
Winston_Sun
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4 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
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4 years ago

Hi Sun,


Could you attached you qar here I try to replicate the issue. If this a bug, I will file ticket to developer. If the the desing is PnC, you can response to my email and attach it there.

What version of Quartus you are using?




  • Winston_Sun's avatar
    Winston_Sun
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    4 years ago

    Hi Syafieq, I've sent the email with qar attached. The project version is QPro v20.4 (I’ve also tried QPro 20.2 before as well, but it gives the same warnings and timing violations). Please note that this design is based on intel’s JESD204C example design. All I modified is to replace the single JESD204C IP block in the intel example design with three separate JESD204C IP blocks (Duplex PHY + Simplex TX MAC + Simplex RX MAC). Also, I noticed that the JESD204C IP’s sdc files in the synth folder (generated by intel during compilation) has the same warnings, ignoring filter signals in the sdc.