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Winston_Sun's avatar
Winston_Sun
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5 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
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5 years ago

Hi Sun,


Could you attached you qar here I try to replicate the issue. If this a bug, I will file ticket to developer. If the the desing is PnC, you can response to my email and attach it there.

What version of Quartus you are using?