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Winston_Sun's avatar
Winston_Sun
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4 years ago

SDC timing constraint cannot be applied during compilation

Hi, I'm currently working on the JESD204C intel FPGA example design on Stratix 10 TX and getting timing violations (fig 1). When I check the warning, it is because the signals are ignored ("could not...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Sun,


Try to remove and add again the script and compile it to see if it reflect any changes


  • Winston_Sun's avatar
    Winston_Sun
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi, I removed and re-add the sdc file to the project (in Project -> Addd/Remove Files in Project...) and compiled, but still shows all the clocks and signals in the sdc file are ignored.

    warning examples:

    Warning (332174): Ignored filter at intel_j204c_ed_rx_tx.sdc(42): u_j204c_rx_tx_ss|jesd204c_duplex_phy|jesd204c_duplex_phy|j204c_phy_hip_inst|inst_xcvr|tx_clkout|ch0 could not be matched with a clock File: /nobackup/wsun2/jesd204c_remove_addr_concat/ADI_SPI_JESD204C_Nios_Styx_test_design/ADI_SPI_JESD204C_TX_design/hardware/ed/rtl/du/intel_j204c_ed_rx_tx.sdc Line: 42

Warning (332174): Ignored filter at intel_j204c_ed_rx_tx.sdc(42): u_j204c_rx_tx_ss|core_pll|core_pll_clk_1x could not be matched with a clock File: /nobackup/wsun2/jesd204c_remove_addr_concat/ADI_SPI_JESD204C_Nios_Styx_test_design/ADI_SPI_JESD204C_TX_design/hardware/ed/rtl/du/intel_j204c_ed_rx_tx.sdc Line: 42

    The top qsys sdc file, intel_j204c_ed_rx_tx.sdc, is shown in qsf file as 

    set_global_assignment -name SDC_FILE ../rtl/du/intel_j204c_ed_rx_tx.sdc